The present invention relates generally to memory devices and in particular the present invention relates to non-volatile memory devices with low or zero power standby modes.
The use of non-volatile memory systems that maintain data integrity when a power supply is removed are expanding rapidly in integrated circuit technology. A class of non-volatile memory systems having memory cells which have a source, a drain, a channel, a floating gate over the channel and a control gate are widely used. Two popular types of non-volatile memory designs in this class are electronically erasable and programmable read only memories (EEPROM) and FLASH erasable-programmable read only memory (EPROM). The FLASH EPROM or flash memory system allows the simultaneous erasure of multiple memory cells.
The floating gate of the memory cell stores data and are generally formed from polysilicon members completely surrounded by an insulator. A flash memory cell is programmed when a charge is stored on the floating gate. Moreover, a memory cell is un-programmed, or erased, when the charge is removed from the floating gate. One method of programming a memory cell is accomplished by applying a positive potential (e.g., 4-7 V) to its drain and a programming potential (e.g., 10-15) to its control gate programs. This causes electrons to be transferred from the source to the floating gate of the memory cell. One method of erasing a memory cell is accomplished by applying a positive potential (e.g., 10-15 V) to its source while grounding the control gate and letting the drain float. This action removes electrons from the floating gate. The programming action of transferring electrons to the floating gate results in a memory cell that conducts less current when read than it would otherwise in the un-programmed state.
In non-volatile complementary metal-oxide semiconductor (CMOS) memories employing floating-gate memory devices, a memory array consisting of a number of these devices is customarily coupled to a common sensing circuit through a column line connecting the drains of the individual memory devices. Word lines are connected to the control gates of the devices in the array, to select the data word to be coupled on the column lines.
During a read operation in non-volatile complementary metal-oxide semiconductor (CMOS) memories employing floating-gate memory devices, an individual word line is selected and asserts a signal on the control gates of the memory cells. The memory cell will conduct current from its source to its drain. The drain is coupled to a column, or bit line. If a cell is programmed, the current is small compared to current conducted by an erased cell. The state of each individual floating gate memory device is then read from the level of current conducted through the column line by a sense amplifier. The individual sense amplifiers/comparators determine the state of the memory device by comparing the column current with a reference current conducted by a reference floating gate memory device that is set to conduct one-half of the current of an un-programmed floating gate memory device. This reference current is generated locally for the sense amplifier by a current mirror circuit that mirrors the current conducted through the reference floating gate memory cell.
When the memory device is in a low power or standby mode, the current mirror reference circuit is turned off and the circuit is put into low power mode. Upon leaving standby mode, the current mirror circuit must bring its output back to operating levels. In so doing, the current mirror output must overcome significant capacitive and parasitic effects. This process has the effect of significantly delaying the time that first access to the non-volatile memory employing floating-gate memory devices can be made after leaving a low power or standby mode.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a system to minimize first access set up time from standby.
The above-mentioned problems with memories and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a memory circuit comprises an array of memory cells arranged in columns using bit lines, a reference current generation circuit provides a reference current, a comparator circuit is coupled to the bit lines to sense bit line current and compare the bit line current to the reference current, and a bias circuit to maintain an operating bias on the reference current generation circuit when the memory is in low power mode.
In another embodiment, a memory device current reference circuit comprises a current reference source, a current mirror circuit, and a standby bias circuit that maintains an operating bias in the current mirror circuit when in a low power mode.
In a further embodiment, a memory system comprises an external processor, and a non-volatile memory coupled to the external processor. The non-volatile memory comprises: an array of memory cells arranged in columns coupled to bit lines, a comparator to compare a bit line current with a reference current and to produce an output signal, a reference current generation and distribution circuit to provide the reference current, and a standby bias circuit to maintain a bias in the reference current generation and distribution circuit when in a low power mode.
In another embodiment, a memory device current reference circuit comprises a reference generation source, a current replication and distribution circuit, and a bias maintenance circuit to maintain an operating bias in the current replication and distribution circuit when the memory device is not in an active mode.
A method of generating and distributing a reference current in a memory device comprising generating a reference current, replicating the reference current in a replication circuit, and maintaining a bias in the replication circuit when in a low power mode.
In yet another embodiment, a memory device sense amplifier comprises a current reference input to receive a reference current, a data input to receive a data input current, a comparator circuit to determine a relative level of the data current with the current reference, and a standby bias circuit to maintain a bias on the comparator circuit when in standby mode.
Another method of sensing a current data signal in a memory device comprising receiving a reference current on a reference current input, receiving a bit line current on a data input, comparing the reference current and the bit line current to determine a relative level, and maintaining a bias on the reference current input when in standby mode.
In yet another embodiment, a memory device current reference circuit comprises a reference circuit with a flash cell to provide a reference current, a reference control circuit to receive the reference current and output a control voltage on a control circuit output, a sense circuit coupled to receive the control voltage and replicate the reference current, and a bias circuit coupled to the control circuit output to maintain a bias during low power operation.
In a further embodiment, a non-volatile memory device comprises a current sense amplifier to compare a bit line current with a reference current, where the current sense amplifier generates the reference current in response to a voltage provided on a voltage connection, and a bias circuit coupled to the voltage connection to provide a bias voltage when the non-volatile memory is in a low power mode.
In yet another embodiment, a non-volatile flash memory comprises an array of non-volatile memory cells, a sense amplifier coupled to compare a bit line current with a reference current conducted through a reference transistor, a reference circuit coupled to a gate of the reference transistor to provide a reference voltage, and a bias circuit coupled to the gate of the reference transistor to provide a bias voltage.
In yet another embodiment, a non-volatile flash memory device comprises a flash memory cell programmed to conduct a reference current, a current mirror control NMOS transistor where a gate is coupled to a source, a drain is coupled to a positive power source, and the source is coupled to the flash memory cell, a current replication transistor where a gate is coupled to the source of the current mirror control NMOS transistor to replicate the reference current, a sense amplifier coupled to a bit line and coupled to the current replication transistor, and a bias circuit coupled to the gate of the current replication transistor to provide a bias voltage.
In another embodiment, a non-volatile flash memory device comprises a flash memory cell programmed to conduct a reference current, a current mirror control transistor coupled to the flash memory cell to sense the reference current and produce a current mirror control output, a current replication transistor where a gate is coupled to receive the current mirror control output and replicate the reference current, a sense amplifier coupled to receive a bit line current and the reference current from the current replication transistor, and a bias circuit coupled to the gate of the current replication transistor to provide a bias voltage.